Early in the history of the semiconductor industry, integrated circuit (IC) design centers and manufacturers generally designed each generation of silicon circuits from scratch. As disadvantages, designing from scratch requires tremendous resources (financial costs, etc.) and time (e.g., many man-years), and such may now represent unacceptable costs and time-to-market (TtM) product delays. That is, in today's competitive, fast-changing semiconductor market, IC design centers and manufacturers must, for the sake of basic business survival, quickly move to “process shift” IC products from one size technology (e.g., 0.18 μm) to the latest deep-submicron sized technology (e.g., 0.13 μm) to provide next generation ICs. One way to quickly do this is to reuse existing technology (e.g., designs) as much as possible to build new silicon systems.
With regard to viable methods for reuse, several are available. For example, a very high-speed IC hardware description language (VHDL) can be used to re-synthesize the circuit, or one can reuse an existing design layout and migrate the layout as it is to new process parameters and constraints. Further elaborating, a design reuse methodology based on migration employs hard intellectual property (IP) design. If reuse of soft and hard IP are compared on a value scale, hard IP is superior because all work for verification and simulation have already been done, and the is already proven as operational in silicon. Such hard IP design will most likely work successfully again if carefully migrated to any next sub-micron process. As a result, engineering time and talent required for reusing hard IP and migrating it to a target process technology will be significantly lower as opposed to building from scratch, or even using soft IP.
As a further advantage of hard IP reuse, the IC design centers and manufacturers can also use the opportunity to further tweak and optimize a hard IP layout during the migration process, e.g, tweak for improved power output, speed (e.g., from 700 MHz to 1 GHz) and more efficient wafer real estate usage (e.g., 30% size reduction). All types of semiconductor circuits and systems can be migrated, for example, microprocessor cores, digital signal processors (DSPs), data path designs, random-access memories (RAMs), read-only memories (ROMs), standard-cell libraries, complete chips, etc.
Based upon the above advantages, the present invention focuses on providing improvements in hard IP reuse arrangements (e.g., apparatus and methodologies) that enable ease and speed in reuse and optimization of hard IP for deep-submicron design., i.e., improvement arrangements for migrating and reusing legacy designs.
[IN ORDER TO GUARANTEE CLARITY OF ONES OF THE ORIGINALLY SUBMITTED BLACK-AND-WHITE DRAWINGS, ENCLOSED HEREWITH AND FORMING PART OF THE ORIGINAL DISCLOSURE OF THIS APPLICATION, ARE COLOR COPIES OF ONES OF THE DRAWING FIGS. FOR THE PURPOSE OF ENHANCING A CLARITY OF THE DRAWINGS UNTIL PROPERLY CROSS-HATCHED FORMAL DRAWINGS CAN BE PREPARED; WITHIN SUCH COLOR DRAWINGS, PINKISH AREAS REPRESENT DIFFUSION AREAS, REDDISH-ORANGE AREAS REPRESENT METAL1 AREAS, BLUISH AREAS REPRESENT POLYSILICON AREAS, YELLOWISH AREAS REPRESENT CONTACTS CONNECTING DIFFUSION TO METAL, AND BLUISH/PINKISH (POLYSILICON/DIFFUSION) OVERLAP AREAS REPRESENT AREAS WHERE ACTIVE GATES OF TRANSISTORS RESIDE.]